High throughput energy efficient multi - FFT architecture on FPGAs ( Draft ) ∗

To process high-rate streaming data, throughput is one of the key performance metrics for FFT design. However, high throughput FFT architectures consume large amount of power due to complex routing or excessive memory access. In this paper, we propose a Cooley-Turkey algorithm based, high throughput energy-efficient multi-FFT architecture. In the proposed architecture, we use multiple time-multiplexed pipeline FFT processors to achieve high throughput. Time-multiplexers instead of routing network are used for shuffling the intermediate data, thus reducing the burden of interconnection power for large FFT problem size. To reduce memory power, a method of dynamic memory activation is developed. For N -point FFT (64 ≤ N ≤ 4096), our designs improve the energy efficiency (defined as GOPS/Joule) by 17% to 26%, compared with a stateof-the-art design. The experimental results show that, for various throughput requirements, the proposed design can achieve 50 ∼ 63 GOPS/Joule, i.e. up to 78% of the estimated peak energy efficiency of FFT designs on FPGAs. Index Terms — Fast Fourier Transform, FPGA computing, High throughput FFT, Energy efficient design